Tekmos now offers replacement parts for many members of the 80C51 family. Based around our internally developed 80C51 core, we now offer replacements for the original Atmel, Intel, and NXP parts. The main family is supported by our 8xC51Rx2 family. Tekmos also supports many specialty versions of the 80C51 produced by NXP. The Tekmos 80C51 core has been carefully designed to duplicate the original 80C51 on a clock for clock basis.
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It is an example of a complex instruction set computer , and has separate memory spaces for program instructions and data.
This made them more suitable for battery-powered devices. Some derivatives integrate a digital signal processor DSP. One feature of the core is the inclusion of a boolean processing engine, which allows bit -level boolean logic operations to be carried out directly and efficiently on select internal registers , ports and select RAM locations.
Another feature is the inclusion of four bank selectable working register sets, which greatly reduce the time required to perform the context switches to enter and leave interrupt service routines. With one instruction, the can switch register banks, avoiding the time-consuming task of transferring the critical registers to RAM. The main program then performs serial reads and writes simply by reading and writing 8-bit data to stacks. As of [update] , new derivatives are still being developed by many major chipmakers, and major compiler suppliers such as IAR Systems , Keil and Altium Tasking  continuously release updates.
The original core ran at 12 clock cycles per machine cycle, with most instructions executing in one or two machine cycles. All Silicon Labs , some Dallas and a few Atmel devices have single cycle cores.
MCS based microcontrollers have been adapted to extreme environments. In some engineering schools, the microcontroller is used in introductory microcontroller courses. The last digit can indicate memory size, e. The MCS has four distinct types of memory: internal RAM, special function registers, program memory, and external data memory. The is designed as a modified Von-Neumann Architecture with segregated memory data and instructions ; it can only execute code fetched from program memory, and has no instructions to write to program memory.
Which is similar to Harvard Architecture. Most systems respect this distinction, and so are unable to download and directly execute new programs. Although the 's architecture is unique; the buses to access both types of memory are the same; only the data bus, the address bus, and the control bus leave the processor.
IRAM from 0x00 to 0x7F can be accessed directly, using an 8-bit absolute address that is part of the instruction. The original has only bytes of IRAM. The added IRAM from 0x80 to 0xFF, which can only be accessed indirectly; direct access to this address range goes to the special function registers. Most clones also have a full bytes of IRAM. The 32 bytes from 0x00—0x1F memory-map the 8 registers R0—R7. Eight bytes are used at a time; two program status word bits select between four possible banks.
They cannot be accessed indirectly via R0 or R1; indirect access to those addresses will access the second half of IRAM.
It may be on- or off-chip, depending on the particular model of chip being used. Program memory is read-only, though some variants of the use on-chip flash memory and provide a method of re-programming the memory in-system or in-application.
External data memory XRAM is a third address space, also starting at address 0, and allowing 16 bits of address space.
It can also be on- or off-chip; what makes it "external" is that it must be accessed using the MOVX move external instruction.
The only register on an that is not memory-mapped is the bit program counter PC. This specifies the address of the next instruction to execute. Relative branch instructions supply an 8-bit signed offset which is added to the PC. Eight general-purpose registers R0—R7 may be accessed with instructions one byte shorter than others. Only eight bytes of that range are used at any given time, determined by the two bank select bits in the PSW.
The following is a partial list of the 's registers, which are memory-mapped into the special function register space:. These are the 16 IRAM locations from 0x20—0x2F, and the 16 special function registers 0x80, 0x88, 0x90, Any bit of these bytes may be directly accessed by a variety of logical operations and conditional branches.
For the former, the most significant bit of the accumulator can be addressed directly, as it is a bit-addressable SFR. For the latter, there are explicit instructions to jump on whether or not the accumulator is zero.
There is also a two-operand compare and jump operation. Instructions are all 1 to 3 bytes long, consisting of an initial opcode byte, followed by up to 2 bytes of operands. The least significant nibble of the opcode selects the primary operand as follows:. The most significant nibble specifies the operation as follows. Not all support all addressing modes; the immediate mode in particular is unavailable when the primary operand is written to.
Instruction mnemonics use destination , source operand order. The irregular instructions comprise 64 opcodes, having more limited addressing modes, plus several opcodes scavenged from inapplicable modes in the regular instructions. The SJMP short jump opcode takes a signed relative offset byte operand and transfers control there relative to the address of the following instruction. One of the reasons for the 's popularity is its range of operations on single bits. Bits are always specified by absolute addresses; there is no register-indirect or indexed addressing.
Instructions that operate on single bits are:. A bit operand is written in the form address. Although most instructions require that one operand is the accumulator or an immediate constant, opcode 0x85 performs MOV directly between two internal RAM locations. There are various high-level programming language compilers for the Several C compilers are available for the , most of which allow the programmer to specify where each variable should be stored in its six types of memory, and provide access to specific hardware features such as the multiple register banks and bit manipulation instructions.
There are many commercial C compilers. Since data could be in one of three memory spaces, a mechanism is usually provided to allow determining to which memory a pointer refers, either by constraining the pointer type to include the memory space, or by storing metadata with the pointer. Intel discontinued its MCS product line in March ;   however, there are plenty of enhanced products or silicon intellectual property added regularly from other vendors.
The 's predecessor, the , was used in the keyboard of the first IBM PC , where it converted keypresses into the serial data stream which is sent to the main unit of the computer. An Intel served a similar role in the Sinclair QL. The and derivatives are still used today [update] for basic model keyboards.
The was a reduced version of the original that had no internal program memory read-only memory , ROM. To use this chip, external ROM had to be added containing the program that the would fetch and execute. A vendor might sell an as an for any number of reasons, such as faulty code in the 's ROM, or simply an oversupply of s and undersupply of s. Most modern compatible microcontrollers include these features. They were identical except for the non-volatile memory type.
This part was available in a ceramic package with a clear quartz window over the top of the die so UV light could be used to erase the EPROM. Enhancements mostly include new and enhanced peripherals. The 80C5x7 has fail-safe mechanisms, analog signal processing facilities, enhanced timer capabilities, and a bit arithmetic peripheral. Other features include:.
OKI M80C More than 20 independent manufacturers produce MCS compatible processors. Atmel AT89C Today, s are still available as discrete parts, but they are mostly used as silicon intellectual property cores. Modern cores are faster than earlier packaged versions. Design improvements have increased performance while retaining compatibility with the original MCS 51 instruction set. The original Intel ran at 12 clock cycles per machine cycle, and most instructions executed in one or two machine cycles.
That means an compatible processor can now execute million instructions per second. In Intel announced the MCS family, an up to 6 times faster variant,  that's fully binary and instruction set compatible with The MCS family was also discontinued by Intel, but is widely available in binary compatible and partly enhanced variants.
It features extended instructions  — see also the programmer's guide  — and later variants with higher performance,  also available as intellectual property IP. The MCS family was also discontinued by Intel, but is widely available in binary compatible and partly enhanced variants from many manufacturers.
This article is based on material taken from the Free On-line Dictionary of Computing prior to 1 November and incorporated under the "relicensing" terms of the GFDL , version 1. From Wikipedia, the free encyclopedia.
Parity, P. Gives the parity XOR of the bits of the accumulator, A. User defined, UD. May be read and written by software; not otherwise affected by hardware. Overflow flag , OV. Set when addition produces a signed overflow. Register select 0, RS0. The low-order bit of the register bank.
Set when banks at 0x08 or 0x18 are in use. Register select 1, RS1. The high-order bit of the register bank. Set when banks at 0x10 or 0x18 are in use. Flag 0, F0. Auxiliary carry , AC. Set when addition produces a carry from bit 3 to bit 4. Carry bit , C.
Microcontrollers - 8051 Architecture
The Intel microcontroller is one of the most popular general purpose microcontrollers in use today. The success of the Intel spawned a number of clones, which are collectively referred to as the MCS family of microcontrollers, which includes chips from vendors such as Atmel, Philips, Infineon, and Texas Instruments. The Intel is an 8-bit microcontroller which means that most available operations are limited to 8 bits. There are 3 basic "sizes" of the Short, Standard, and Extended.
Embedded Systems/8051 Microcontroller