It has eight output pins which increments from zero to eight for every input clock pulse. The maximum clock frequency is 5Mhz and is commonly used in digital counters, LED drivers, and other digital arithmetic applications. These are the 8 output pins on which the counting occurs, they are not in order hence verify pin diagram above. The counting happens when this clock pulse goes high , this pin is normally connected to timer or other uC to produce a pulse. The IC CD is used for counting applications, it has the capability to turn on 8 outputs sequentially in a pre-defined time and reset the count or hold it when required. It also has the capability to indicate the status of counting using Carry pin.
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These counters are advanced one count at the positive clock sig-. Use of the Johnson counter configuration permits. Anti-lock gating is provided, thus assuring. The decoded output are normally low. OUT signal completes one cycle every 10 clock input cycles in. CDBMS and is used to ripple-clock the succeeding device. Braze Seal DIP. Frit Seal DIP.
Ceramic Flatpack. Functional Diagrams. FN Rev 0. August Rev 0. VSS 8. Page 1 of Absolute Maximum Ratings. Input Voltage Range, All Inputs. Operating Temperature Range. Lead Temperature During Soldering. Reliability Information. Thermal Resistance. Flatpack Package. Device Dissipation per Output Transistor. Junction Temperature. TABLE 1. Supply Current. Input Leakage Current. Output Voltage. Output Current Sink. Output Current Source. N Threshold Voltage.
P Threshold Voltage. Input Voltage Low. Note 2. Input Voltage High. NOTES: 1. For accuracy, voltage is measured differentially to VDD. Limit is. Page 2 of Schmitt trigger action in the CLOCK input circuit provides pulse shaping that allows unlimited clock input pulse rise and fall times. Use of the Johnson counter configuration permits high speed operation, 2-input decode gating and spike-free decoded outputs. Anti-lock gating is provided, thus assuring proper counter sequence.
The decoded output are normally low and go high only at their respective decoded time slot. Each decoded output remains high for one full clock cycle. Limit is plemented.
CD4022BMS Counter/Dividers. Datasheet pdf. Equivalent