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This page contains resource utilization data for several configurations of this IP core. The data is separated into a table per device family. In each table, each row describes a test case. The columns are divided into test parameters and results. The test parameters include the part information and the core-specific configuration parameters. Any configuration parameters that are not listed have their default values; any parameters with a blank value are disabled or set automatically by the IP core.

Copyright Xilinx, Inc. Arm is a registered trademark of Arm Limited in the EU and other countries. All other trademarks are the property of their respective owners. The information disclosed to you hereunder the "Materials" is provided solely for the selection and use of Xilinx products.

Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent.


AXI Datamover

Zynq platform Shi Sai company of SEL Xilinx release based on the full SoC SystemonChip able to programme of Xilinx, SOC system on a chip industry first easily extensible processing platform of framework, by the software programmable ability of processor and FPGA FieldProgrammableGateArray, ready-made programmable gate array hardware programmable capability perfect adaptation, beyond challenge system performance is realized with the system advantage such as low-power consumption and low cost, dirigibility, extensibility, for diversified market provides solution widely, relate generally to video acquisition and process, high-speed communication, digital display circuit and the signal intensive applications such as high-throughput bridge joint. In order to play the superior function of Zynq platform, usually need by PS and PL with the use of, hardware accelerator is realized in PL, solve the time consuming parts such as computation-intensive, the part such as data acquisition transmission, system flow control is mainly realized in PS, thus, the problem that PS and PL carries out data interaction is inevitably run into. Goal of the invention: the present invention is directed to the deficiencies in the prior art, proposes a kind of on Zynq platform, realizes the device that PS and PL carries out large data interaction. Described FIFO memory is the synchronization fifo of AXI stream interface, and interface data bus is 32, and the degree of depth is bytes. Described register Read-write Catrol module contains 12 registers, for storing the parameter and transmission state that need in AXIDataMover unit transmission data. Described disposal system is monitored by the register control data transmission in read-write register Read-write Catrol module and transmission state, comprises the steps:.

HS0001 PDF

Resource Utilization for AXI DataMover v5.1


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